Many portable electronic devices such as cameras, cellular telephones, personal digital assistants (PDAs), MP3 players, computers and other devices include an imager for capturing images. One example of an imager is a complementary metal-oxide semiconductor (“CMOS”) imager. A CMOS imager includes a focal plane array of pixels, each one of the pixels including at least one photosensor overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to a storage region.
Typically, each pixel has corresponding readout circuitry that includes at least a charge storage node connected to the gate of the output transistor, such as an output source follower transistor, a reset transistor for resetting the charge storage node to a predetermined charge level, and a row control transistor for selectively connecting the readout circuitry to an output column line. The charge storage node may be constructed as a floating diffusion node. Each pixel may have independent readout circuitry, or may employ common element pixel architecture (CEPA), that may include multiple pixels sharing a single set of readout circuitry.
A pixel (including a photosensor), and its corresponding readout circuitry, are herein collectively referred to as a “pixel circuit.” In a typical CMOS imager, the active elements of a pixel circuit perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel circuit for readout; and (6) output and amplification of a signal representing a reset level and pixel charge. Photo charge may be amplified when the charge moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
FIG. 1 illustrates a typical four-transistor (4T) pixel circuit 100 utilized in a pixel array of an imager, such as a CMOS imager. Pixel circuit 100 includes a pixel having a photosensor 102 (e.g., a photodiode, pinned photodiode, photogate, or photoconductor) and a transfer transistor 104. Pixel circuit 100 also includes readout circuitry, including a charge storage region configured as a floating diffusion node 110, a reset transistor 106, a source follower transistor 108, and a row select transistor 112. Photosensor 102 is connected to floating diffusion node 110 by the transfer transistor 104 when transfer transistor 104 is activated by a transfer control signal TX. Reset transistor 106 is connected between floating diffusion node 110 and an array pixel supply voltage VBIAS. A reset control signal RST is used to activate reset transistor 106, which resets floating diffusion node 110 to a predetermined reset voltage corresponding to the array pixel supply voltage VBIAS, as is known in the art.
Source follower transistor 108 has its gate connected to floating diffusion node 110 and is connected between array pixel supply voltage VBIAS and row select transistor 112. Source follower transistor 108 converts the charge stored at floating diffusion node 110 into an electrical output signal. Row select transistor 112 is controllable by a row select signal RS for selectively outputting an output signal from source follower transistor 108 onto an output column line 114. In a CMOS imager, two output signals are conventionally generated for each pixel circuit; one being a reset signal VRST generated after the floating diffusion node 110 is reset, the other being an image or photo signal VOUT generated after charges are transferred from photosensor 102 to floating diffusion node 110. This process is commonly referred to as “correlated double sampling” or “CDS”. Output signals VRST, VOUT are selectively stored in a sample and hold circuit (not shown).
There is demand for scaled-down pixel sizes, and thus floating diffusion nodes with lower charge storage capacity are being seen. Conventional pixel circuits, however, suffer from an intrinsic limitation due to a trade-off between full-well charge capacity and image lag. The full-well charge capacity of a pixel is a maximum number of electrons that can be generated and stored in a photosensor. When the number of generated electrons reaches the full-well charge capacity, a photosensor is saturated and is unable to further respond to incident photons. Thus, photosensors with higher full-well charge capacity are typically desirable.
Lower capacity floating diffusion nodes, however, can limit the capability of achieving an accurate signal corresponding to a charge near the full-well charge capacity of the photosensor. For example, when the full-well capacity of a photosensor is larger than the charge holding capacity of the corresponding floating diffusion node, there is charge sharing during charge transfer between the photosensor and the floating diffusion node, which can cause image lag. While the full-well charge capacity of the photosensor, or the amount of charge transferred to the floating diffusion node, may be limited, such as through an anti-blooming transistor, this limits the overall dynamic range of the pixel.
Typically, as full-well capacity of a photosensor in a pixel circuit is increased, image lag is also likely to increase. This is due to conventional pixel circuit's reliance on perfect charge transfer (e.g., via a transfer transistor) from a photosensor to a floating diffusion region. FIGS. 2A-2C depict an exemplary charge transfer operation between a photosensor 202 and a floating diffusion node 210 of a typical 4T CMOS pixel circuit, such as pixel circuit 100 (FIG. 1). The full-well charge capacity of the pixel is illustrated by shaded area 220. In a pixel where photosensor 202 is a pinned photodiode, this area 220 is determined approximately by the pinned potential VPIN of photodiode 202 and the photodiode capacity CPD. Typically during the light integration period, the charge generated in pinned photodiode 202 is blocked from being transferred to a floating diffusion node 210 by a transfer transistor 204 (e.g., transfer transistor 104 of pixel circuit 100 in FIG. 1) being in an “OFF” state.
The ability to store electrons in floating diffusion node 210 (i.e., when the electrons from photosensor 202 are transferred to floating diffusion node 210 across transfer transistor 204) is determined by the charge holding capacity of the floating diffusion node 210. As shown in FIG. 2B, when the full-well capacity 220 of photosensor 202 is larger than the charge holding capacity of the floating diffusion node 210, there is charge sharing between the photosensor 202 and floating diffusion node 210 when transfer transistor 204 is turned “ON”. In this case, when transfer transistor 204 goes back to the “OFF” state (as shown in FIG. 2C), photosensor 202 will retain signal charge which mixes with generated signal charge of the next frame, causing image lag.
As the full-well charge capacity is increased, for example by increasing pinned potential VPIN of pinned photodiode 202, lag increases, and fixed pattern noise of the pixel is increased, particularly at low lighting levels. Thus, there is need for a pixel circuit with adequate full-well charge capacity, yet with reduced negative effects of lag and fixed pattern noise.
Furthermore, it may be desirable for multiple pixels to use common output circuitry elements in a pixel circuit, such as a common floating diffusion node. An example of multiple pixels in a pixel circuit sharing a common floating diffusion node and readout circuitry is disclosed in U.S. Published Patent Application No. 2006-0256221 A1, filed on May 11, 2005, and assigned to Micron Technology, Inc., the entire disclosure of which is hereby incorporated by reference. Multiple pixels sharing a common floating diffusion node increase the fill factor of a pixel array, and also enable operations such as summing of pixel signals from multiple pixels. Pixel-sharing operations on the same floating diffusion node in a conventional pixel circuit require that the floating diffusion node have an adequate capacity to store charge from all pixels. Further, operations such as pixel summing require a floating diffusion node capacity sufficient to accommodate summed charge from multiple pixels. Operations such as pixel summing, when performed on a pixel circuit with inadequate floating diffusion node capacitance, can degrade the conversion gain of the pixel circuit. Thus, there is a need for a pixel circuit configuration where the conversion gain is not limited by the capacity of the shared floating diffusion node.